Responsibilities:

• Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications

• Design and develop verification testbenches using industry-standard verification languages and methodologies

• Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability

• Review and analyze verification results, and provide feedback to design teams

• Collaborate with design and layout teams to identify and resolve design issues

• Develop new verification methodologies, tools, and techniques, ensuring scalability and portability

• Sign-off mixed signal designs in preparation for tapeout

• Write behavioral models from custom analog and mixed-signal circuits in SystemVerilog HDL

• Collaborate with circuit design teams to understand fine details of custom circuits

• Collaborate with Design Verification team to craft hooks into the behavioral models for effective verification

• Run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits

• Write scripts and simple tools for automating repetitive tasks

• Optimize and refine models to ensure accuracy while maintaining efficient simulation performance

• Review and analyze verification results, and provide feedback to design team

• Document modeling techniques and results for internal and external dissemination

• Keep updated with industry trends in modeling techniques

Requirements:

• Bachelor's degree in Electrical Engineering and 5+ years of relevant industry experience or equivalent

• Strong understanding of analog and mixed-signal circuit design and verification
  principles

• Ability to write test plans, present results, and communicate clearly with multi-functional teams

• Have a familiarity with verification methodologies and tools: simulators, waveform
  viewers, execution automation, simulation time optimization, and coverage collection

• Familiarity with analog behavioral models is a plus

• Deep knowledge of Verilog/SystemVerilog with ability to write synthesize-able and behavioral code

• Deep knowledge of digital logic gates, clocking and state elements

• Deep knowledge of SPICE simulation, HDL simulation and logic equivalence tools

• Working understanding of analog circuit architecture such as ADC, DAC, LDO, Charge pump, etc.

• Have good programming skills and can write efficient programs or scripts in Perl, Python, and/or C

• Excellent debugging, problem-solving and analytical skills

• Strong communication and teamwork skills

Salary Range: $110,000 - $300,000 / year